1. Field of Use
This invention relates to memory systems containing semiconductor memory elements including those in which stored information must be periodically refreshed to preserve the integrity of such information.
2. Prior Art
It is well known to construct memory systems from a number of memory modules. In certain prior art systems, memory modules are paired together to provide a double word fetch access capability. The term double word fetch access as used herein refers to the capability of being able to access a pair of words at a time from a memory system during a cycle of operation. This type of system is described in the copending patent application "System Providing Multiple Fetch Bus Cycle Operation", invented by John L. Curley, Robert B. Johnson, Richard A. Lemay and Chester M. Nibby, Jr., Ser. No. 867,270, filed on Jan. 5, 1978, now U.S. Pat. No. 4,236,203 issued on Nov. 25, 1980, and assigned to the same assignee as named herein.
In the above prior art system, the memory system connects to an asynchronously operated single word wide bus. In the arrangement, a request for multiple words is made in a single bus cycle and the requested information words are delivered to the bus over a cycle of operation which consists of a series of response cycles.
It has been found that in order to maximize transfers, it is desirable to be able to transfer a pair of words over a double wide bus during a single bus cycle. To achieve this mode of operation, it is necessary to provide a memory system which is able to access both module units simultaneously. Such an arrangement is described in the cited related copending patent application "Sequential Chip Select Decode Apparatus and Method".
For compatibility purposes, it is desired that the double wide bus system perform double fetch operations. This necessitates that two types of memory systems be connected into the system. Accordingly, such systems have the disadvantage of increased complexity high cost and increased maintenance.
Accordingly, it is a primary object of the present invention to provide a memory subsystem which is compatible with systems which incorporate a double fetch capability.
It is a further object of the present invention to provide a memory subsystem capable of operating in more than one mode and which can be implemented within a minimum of circuits.